In systems having internal voltage regulators providing an internal power supply for a digital core, the internal power supply VDD may act totally independently from the power supply HDVDD for I/O functional elements. Often this internal power supply VDD is connected to an external capacitor and VDD is subject to external short circuits. Short circuit at VDD could result in a floating condition at the inputs to the I/O circuits and harmful extraneous currents flowing through the I/O from its power supply. It is imperative to detect this short circuit condition on the internal supply to set the I/O functions into a high impendence (HiZ) state eliminating floating inputs.
FIG. 1 illustrates a typical protection circuit of prior art. The internal voltage regulator 101, often based on a band gap temperature compensated reference, provides the power VDD 105 for core logic 108. External supply voltage HVDD 110 supplies all circuitry operating at nominal VDD range including I/O circuits 104 supplied from a separate external device pin HVDD 112. The power supply includes an internal capacitor 111 and an external pin 113 for attachment of an external capacitor. Internal voltage regulator 101 and I/O circuits 104 are powered between HVDD supply 110 and ground 100. Core logic 108 is powered between VDD supply and ground 100. Differential analog comparator 102 detects a low voltage on VDD at input 105. Differential analog comparator 102 has an inverting input 105 receiving VDD and a non-inverting input 109 receiving a reference voltage VREF. Upon the occurrence of a low voltage at input 105, analog comparator 102 produces a rapid high going signal at output 106. This drives inverter 103 producing a low at node 107, the active low HiZ_input to I/O circuits 104. This active low HiZ_input places I/O circuits 104 in an off condition.
There are two conceivable scenarios for VDD supply failures. The first scenario is DROOP, where supply VDD drops so slowly there is enough time to develop reset signals of sufficient amplitude. The second scenario is SHORT, where VDD drops immediately as by a short circuit. This drop is so fast that reset signals do not have enough time to attain sufficient amplitude. In this case no circuit supplied from VDD is reliable. The I/O control signals from the core logic 108 are then considered as invalid.
Protection against unsafe power supply conditions requires effective detection that operates under failing VDD conditions that include extremely slow decay of VDD or moderate to fast changes resulting in VDD approaching 0.0 volts. Protection also must gate all I/O circuits into a HiZ condition when any potentially destructive power supply failure mechanisms in either VDD or HVDD are detected.